/*
Title: Bus Activity Monitor to Uart Package
Author: Rajas Mokashi
Created for: ECE510: System Verilog Final Project
Description: This is the package used by the Uart Port(module).
*/

package UARTPackage;
  
  parameter   CLOCKFREQ       = 8064000;              // Make sure CLOCKFREQ is atleast the LCM of all supported baud rates
  localparam  Baud300Count    = (CLOCKFREQ/300)/2;
  localparam  Baud600Count    = (CLOCKFREQ/600)/2;
  localparam  Baud1200Count   = (CLOCKFREQ/1200)/2;
  localparam  Baud2400Count   = (CLOCKFREQ/2400)/2;
  localparam  Baud9600Count   = (CLOCKFREQ/9600)/2;
  localparam  Baud14400Count  = (CLOCKFREQ/14400)/2;
  localparam  Baud19200Count  = (CLOCKFREQ/19200)/2;
  localparam  Baud28800Count  = (CLOCKFREQ/28800)/2;
  localparam  Baud38400Count  = (CLOCKFREQ/38400)/2;
  localparam  Baud56000Count  = (CLOCKFREQ/56000)/2;
  localparam  Baud57600Count  = (CLOCKFREQ/57600)/2;
  localparam  Baud115200Count = (CLOCKFREQ/115200)/2;
  
  typedef enum {TIdle,TStart,TBit1,TBit2,TBit3,TBit4,TBit5,TBit6,TBit7,TBit8,TStopBit1,TStopBit2}TransmitStates;
  
  typedef enum {RIdle,RBit1,RBit2,RBit3,RBit4,RBit5,RBit6,RBit7,RBit8,RStopBit1,RStopBit2}RecieveStates;
      
endpackage